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@@ -30,6 +30,8 @@
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],
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)
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#set text(11pt)
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#let pTypeFill = rgb("#dd5959").lighten(10%);
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#let nTypeFill = rgb("#5997dd").lighten(10%);
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@@ -37,7 +39,7 @@
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[Digitaltechnik]
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))
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#let SeperatorLine = line(length: 100%, stroke: (paint: black, thickness: 0.3mm))
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#let SeperatorLine = line(length: 100%, stroke: (paint: black, thickness: 0.2mm))
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#let MathAlignLeft(e) = {
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align(left, block(e))
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}
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@@ -201,101 +203,108 @@
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#bgBlock(fill: colorOptimierung)[
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#subHeading(fill: colorOptimierung)[Quine McCluskey]
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=== Quine
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1. KNF/DNF $->$ KKNF/KDNF
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2. Primiplikant Bestimme \
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2.1. Terme nach positive Literal ($x_i$) soltieren\
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2.2. Abosbition zwischen zwei unterliegen Blöcken \
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Eine Literal unterschied, #raw("X") müssen matchen \
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2.3. Abhacken was absorbiert wurde \
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#image("../images/digitaltechnik/qmc6.jpg", height: 3cm)
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#SeperatorLine
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=== MacCluskyn
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=== McClusky
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1. Überdeckungstabelle aufstellen
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#image("../images/digitaltechnik/qmc1.jpg", height: 3cm)
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#SeperatorLine
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2. Kernprimimplikanten finden \
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(Splaten mit nur einem Eintrag) \
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und vom Kerprimiplaten übdeckte \
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NICHT Kernprimstplaten Streichen
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#image("../images/digitaltechnik/qmc3.jpg", height: 3cm)
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#SeperatorLine
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3. Splaten dominazen \
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(Dominierende Splate streichen)
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(Dominierte Spalte streichend)
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#image("../images/digitaltechnik/qmc4.jpg", height: 3cm)
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#SeperatorLine
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4. Zeilen dominazen \
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(Domenierete Zeile streiche) \
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Kosten: D1 dominierte D2 \
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D1 $<=$ D2 $->$ NUR dann streichen \
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#image("../images/digitaltechnik/qmc5.jpg", height: 3cm)
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#SeperatorLine
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5. Wiederhole 3.-5. solange noch was geht
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]
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#bgBlock(fill: colorState)[
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#subHeading(fill: colorState)[Latches, Flipflops und Register]
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#image("../images/digitaltechnik/dlatch2.jpg", height: 6cm)
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]
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#bgBlock(fill: colorState)[
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#subHeading(fill: colorState)[Pipeline/Parallele Verarbeitungseinheiten]
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// Dotierung
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#image("../images/digitaltechnik/pipeline1.jpg")
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#image("../images/digitaltechnik/pipeline2.jpg")
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#image("../images/digitaltechnik/parallel.jpg", height: 3cm)
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]
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#bgBlock(fill: colorState)[
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#subHeading(fill: colorState)[Zustandsautomaten]
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]
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]
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#pagebreak()
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#columns(2, gutter: 2mm)[
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// Mosfet
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#bgBlock(fill: colorRealsierung)[
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#table(
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columns: (auto, 1fr),
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[N-Type],
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#subHeading(fill: colorRealsierung)[FET/MOSFET Funktion]
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#grid(columns: (1fr, 2fr),
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image("../images/digitaltechnik/gateWidth.jpg", height: 3cm),
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[
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- Dotierung: Phosphor (V)
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- Negative Ladgunsträger ($e^-$)
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- mehr Elektron als Si
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],
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[P-Type],
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[
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- Dotierung: Bor (III)
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- Postive Landsträger (Löcher)
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- mehr Löcher als Si
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#grid(columns: (1fr, 1fr),
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row-gutter: 2.5mm,
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[$W$: Kanalweite], [$L$: Kanallänge],
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[Löcherbeweglichkeit: $mu_"n/p"$],
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[Oxdy Dicke: $t_"ox"$],
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[Oxdy Dielektriukum: $epsilon_"ox"$],
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[$mu_"n" = 1,6 mu_"p" "bis" 3,5 mu_"p"$],
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)
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$L$ wir immer so kleine wie möglich gewählt $= L_"min"$
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$beta_"n/p" = (mu_"n/p" epsilon_0 epsilon_"ox")/(t_"ox") W/L = K'_"n/p" W/L$
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$R_"on" = $
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]
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)
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#table(columns: (1fr, 1fr),
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fill: (x, y) => if (calc.rem(y, 2) == 1) { tableFillLow } else { tableFillHigh },
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#zap.circuit({
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import cetz.draw : *
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import zap : *
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[*NMOS*], [*PMOS*],
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diode("A", (0,1.7), (3,1.7), fill: black, i: (content: $i_d$, anchor: "south"))
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image("../images/digitaltechnik/nmos3.jpg"),
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image("../images/digitaltechnik/pmos3.jpg"),
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[
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- Source am *niedrigen* Potenzial (*GND*)
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- Guter PULL-DOWN
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],
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[
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- Source am *hohes* Potenzial (*$V_"DD"$*)
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- Guter PULL-UP
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],
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rect((0,0),(1,1), fill: pTypeFill, stroke: none)
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rect((2,0),(3,1), fill: nTypeFill, stroke: none)
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rect((1,0), (1.5,1), fill: color.lighten(pTypeFill, 50%), stroke: none)
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rect((1.5,0), (2,1), fill: color.lighten(nTypeFill, 50%), stroke: none)
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line((2, 0), (2, 1), stroke: (dash: "dotted"))
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line((1, 0), (1, 1), stroke: (dash: "dotted"))
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line((1.5, 0), (1.5, 1), stroke: (dash: "densely-dotted"))
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cetz.decorations.brace((2,-0.1),(1,-0.1))
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content((1.5, -0.6), "RLZ")
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content((2.5, 0.5), "N")
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content((0.5, 0.5), "P")
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content((1.25, 0.5), "-")
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content((1.75, 0.5), "+")
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})
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#grid(
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columns: (1fr, 1fr),
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column-gutter: 6mm,
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align: center,
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[#align(center)[*NMOS*]], [#align(center)[*PMOS*]],
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grid.cell(inset: 2mm,
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align(center,
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zap.circuit({
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import "../lib/circuit.typ" : *
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registerAllCustom();
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fet("T", (0,0), type: "N", scale: 150%);
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})
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)
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),
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grid.cell(inset: 2mm,
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align(center,
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zap.circuit({
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import "../lib/circuit.typ" : *
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registerAllCustom();
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fet("T", (0,0), type: "P", scale: 150%);
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}),
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)
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),
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scale(
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align(center+horizon, scale(
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x: 75%, y: 75%,
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zap.circuit({
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import cetz.draw : *
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@@ -320,8 +329,8 @@
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content((1, 0.5), "D")
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content((2, 0.5), "G")
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})
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),
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scale(
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)),
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align(center+horizon,scale(
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x: 75%, y: 75%,
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zap.circuit({
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||||
import cetz.draw : *
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@@ -346,36 +355,308 @@
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content((1, 0.5), "D")
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content((2, 0.5), "G")
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})
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),
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)
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)),
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*Drain Strom:*
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NMOS: $I_"Dn" = cases(
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block( inset: (top: 2mm, bottom: 2mm),$ I_"Dn" = cases(
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gap: #0.6em,
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0 & 0 < U_"GS" < U_t,
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beta_n (U_"GS" - U_t - U_"DS" / 2) U_"DS" quad & cases(delim: #none, U_"GS" >= U_t, 0 < U_"DS" < U_"GS" - U_t),
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beta_n/2 (U_"GS" - U_"th")^2 & cases(delim: #none, U_"GS" >= U_t, U_"DS" > U_"GS" - U_t)
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)$
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PMOS: $I_"Dp" = cases(
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)$),
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block( inset: (top: 2mm, bottom: 2mm), $I_"Dp" = cases(
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gap: #0.6em,
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0 & 0 > U_"GS" > U_t,
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beta_p (U_"GS" - U_t - U_"DS" / 2) U_"DS" quad & cases(delim: #none, U_"GS" <= U_t, 0 > U_"DS" > U_"GS" - U_t),
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beta_p/2 (U_"GS" - U_"th")^2 & cases(delim: #none, U_"GS" <= U_t, U_"DS" < U_"GS" - U_t)
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)
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$
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)$),
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grid(
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columns: (auto, auto),
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column-gutter: 2mm,
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image("../images/digitaltechnik/nmos1.jpg", height: 2.5cm),
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image("../images/digitaltechnik/nmos2.jpg", height: 2.5cm),
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),
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grid(
|
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columns: (auto, auto),
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column-gutter: 2mm,
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image("../images/digitaltechnik/pmos1.jpg", height: 2.5cm),
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image("../images/digitaltechnik/pmos2.jpg", height: 2.5cm),
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),
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)
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]
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#colbreak()
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// NMOS/PMOS
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#bgBlock(fill: colorRealsierung)[
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#subHeading(fill: colorRealsierung)[CMOS]
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$hat(=)$ Complemntary MOS
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#columns(2, gutter: 2mm)[
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// Dotierung
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#bgBlock(fill: colorRealsierung)[
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#subHeading(fill: colorRealsierung)[Dotierung]
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||||
#table(
|
||||
columns: (auto, 1fr),
|
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[N-Type],
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[
|
||||
- Dotierung: Phosphor (V)
|
||||
- Negative Ladgunsträger ($e^-$)
|
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- mehr Elektron als Si
|
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],
|
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[P-Type],
|
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[
|
||||
- Dotierung: Bor (III)
|
||||
- Postive Landsträger (Löcher)
|
||||
- mehr Löcher als Si
|
||||
]
|
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)
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#table(
|
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columns: (1fr, 1fr),
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zap.circuit({
|
||||
#zap.circuit({
|
||||
import cetz.draw : *
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import zap : *
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||||
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diode("A", (0,1.7), (3,1.7), fill: black, i: (content: $i_d$, anchor: "south"))
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rect((0,0),(1,1), fill: pTypeFill, stroke: none)
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rect((2,0),(3,1), fill: nTypeFill, stroke: none)
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rect((1,0), (1.5,1), fill: color.lighten(pTypeFill, 50%), stroke: none)
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rect((1.5,0), (2,1), fill: color.lighten(nTypeFill, 50%), stroke: none)
|
||||
line((2, 0), (2, 1), stroke: (dash: "dotted"))
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line((1, 0), (1, 1), stroke: (dash: "dotted"))
|
||||
line((1.5, 0), (1.5, 1), stroke: (dash: "densely-dotted"))
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||||
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cetz.decorations.brace((2,-0.1),(1,-0.1))
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content((1.5, -0.6), "RLZ")
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content((2.5, 0.5), "N")
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content((0.5, 0.5), "P")
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content((1.25, 0.5), "-")
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content((1.75, 0.5), "+")
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})
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|
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/*
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#grid(
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columns: (1fr, 1fr),
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column-gutter: 6mm,
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align: center,
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[#align(center)[*NMOS*]], [#align(center)[*PMOS*]],
|
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grid.cell(inset: 2mm,
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align(center,
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zap.circuit({
|
||||
import "../lib/circuit.typ" : *
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|
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registerAllCustom();
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fet("T", (0,0), type: "N", scale: 150%);
|
||||
})
|
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)
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),
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grid.cell(inset: 2mm,
|
||||
align(center,
|
||||
zap.circuit({
|
||||
import "../lib/circuit.typ" : *
|
||||
|
||||
registerAllCustom();
|
||||
fet("T", (0,0), type: "P", scale: 150%);
|
||||
}),
|
||||
)
|
||||
),
|
||||
scale(
|
||||
x: 75%, y: 75%,
|
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zap.circuit({
|
||||
import cetz.draw : *
|
||||
import zap : *
|
||||
rect((1.5,0),(4-1.5, 0.1), fill: rgb("#535353"), stroke: none)
|
||||
rect((0,0),(4,-1), fill: pTypeFill, stroke: none)
|
||||
rect((0.5,-0),(1.5, -0.5), fill: nTypeFill, stroke: none)
|
||||
rect((4 - 1.5,-0),(4-0.5, -0.5), fill: nTypeFill, stroke: none)
|
||||
rect((1.5,-0),(2.5, -0.5), fill: none, stroke: (paint: black, dash: "dotted", thickness: 0.06))
|
||||
|
||||
line((3, 0.3), (3, 0))
|
||||
line((1, 0.3), (1, 0))
|
||||
line((2, 0.3), (2, 0.1))
|
||||
|
||||
cetz.decorations.brace((2.5,-0.6),(1.5,-0.6))
|
||||
content((2, -1.3), "Channel")
|
||||
content((3, -0.25), $"n"^+$)
|
||||
content((1, -0.25), $"n"^+$)
|
||||
content((0.5, -0.75), "p")
|
||||
|
||||
content((3, 0.5), "S")
|
||||
content((1, 0.5), "D")
|
||||
content((2, 0.5), "G")
|
||||
})
|
||||
),
|
||||
scale(
|
||||
x: 75%, y: 75%,
|
||||
zap.circuit({
|
||||
import cetz.draw : *
|
||||
import zap : *
|
||||
rect((1.5,0),(4-1.5, 0.1), fill: rgb("#535353"), stroke: none)
|
||||
rect((0,0),(4,-1), fill: nTypeFill, stroke: none)
|
||||
rect((0.5,-0),(1.5, -0.5), fill: pTypeFill, stroke: none)
|
||||
rect((4 - 1.5,-0),(4-0.5, -0.5), fill: pTypeFill, stroke: none)
|
||||
rect((1.5,-0),(2.5, -0.5), fill: none, stroke: (paint: black, dash: "dotted", thickness: 0.06))
|
||||
|
||||
line((3, 0.3), (3, 0))
|
||||
line((1, 0.3), (1, 0))
|
||||
line((2, 0.3), (2, 0.1))
|
||||
|
||||
cetz.decorations.brace((2.5,-0.6),(1.5,-0.6))
|
||||
content((2, -1.3), "Channel")
|
||||
content((3, -0.25), $"p"^+$)
|
||||
content((1, -0.25), $"p"^+$)
|
||||
content((0.5, -0.75), "n")
|
||||
|
||||
content((3, 0.5), "S")
|
||||
content((1, 0.5), "D")
|
||||
content((2, 0.5), "G")
|
||||
})
|
||||
),
|
||||
)
|
||||
*/
|
||||
]
|
||||
|
||||
// CMOS Circits
|
||||
#bgBlock(fill: colorRealsierung)[
|
||||
#subHeading(fill: colorRealsierung)[CMOS]
|
||||
$hat(=)$ Complemntary MOS
|
||||
|
||||
#table(
|
||||
columns: (1fr, 1fr),
|
||||
zap.circuit({
|
||||
import zap : *
|
||||
import cetz.draw : content
|
||||
import "../lib/circuit.typ" : *
|
||||
|
||||
set-style(wire: (stroke: (thickness: 0.025)))
|
||||
|
||||
registerAllCustom();
|
||||
fet("N0", (0,0), type: "N", angle: 90deg);
|
||||
fet("P0", (0,1), type: "P", angle: 90deg);
|
||||
wire("N0.G", (rel: (-0.1, 0)), (horizontal: (), vertical: "P0.G"), "P0.G")
|
||||
|
||||
node("outNode", (0,0.5))
|
||||
node("inNode", (-0.6,0.5))
|
||||
wire((-1, 0.5), "inNode")
|
||||
wire((0.2, 0.5), "outNode")
|
||||
|
||||
node("N2", (0,-0.5))
|
||||
node("N2", (0,1.5))
|
||||
|
||||
wire((-1, -0.5), (0.5, -0.5))
|
||||
wire((-1, 1.5), (0.5, 1.5))
|
||||
|
||||
content((-1, 0.5), scale($"X"$, 60%), anchor: "east")
|
||||
content((0.45, 0.5), scale($overline("X")$, 60%), anchor: "east")
|
||||
content((-0.9, 1.5), scale($"U"_"DD"$, 60%), anchor: "east")
|
||||
content((-0.9, -0.5), scale($"GND"$, 60%), anchor: "east")
|
||||
}),
|
||||
|
||||
[
|
||||
*Inverter*
|
||||
|
||||
$overline(X)$
|
||||
],
|
||||
|
||||
zap.circuit({
|
||||
import zap : *
|
||||
import cetz.draw : content
|
||||
import "../lib/circuit.typ" : *
|
||||
|
||||
set-style(wire: (stroke: (thickness: 0.025)))
|
||||
|
||||
registerAllCustom();
|
||||
fet("P0", (0.5,0.25), type: "P", angle: 90deg);
|
||||
fet("P1", (0.5,1.25), type: "P", angle: 90deg);
|
||||
fet("N0", (0,-1), type: "N", angle: 90deg);
|
||||
fet("N1", (1,-1), type: "N", angle: 90deg);
|
||||
|
||||
content((-0.7, 1.75), scale($"V"_"DD"$, 60%), anchor: "east")
|
||||
content((-0.7, -1.5), scale($"GND"$, 60%), anchor: "east")
|
||||
|
||||
content("N0.G", scale($"B"$, 60%), anchor: "east")
|
||||
content("P0.G", scale($"B"$, 60%), anchor: "east")
|
||||
content("N1.G", scale($"A"$, 60%), anchor: "east")
|
||||
content("P1.G", scale($"A"$, 60%), anchor: "east")
|
||||
|
||||
wire((-0.75, -1.5), (1.5, -1.5))
|
||||
wire((-0.75, 1.75), (1.5, 1.75))
|
||||
|
||||
wire("N0.S", "N1.S")
|
||||
node("N2", "P0.D")
|
||||
wire("N2", (horizontal: (), vertical: "N0.S"))
|
||||
node("N3", "N0.D")
|
||||
node("N4", "N1.D")
|
||||
node("N5", "P1.S")
|
||||
node("N6", (horizontal: (), vertical: "N0.S"))
|
||||
|
||||
wire("N2", (horizontal: (rel: (0.5, 0)), vertical: "N2"))
|
||||
|
||||
content((horizontal: (rel: (0.65, 0)), vertical: "N2"), scale($"Y"$, 60%))
|
||||
}),
|
||||
|
||||
[
|
||||
*NOR*
|
||||
|
||||
$overline(A +B) = Y$
|
||||
],
|
||||
|
||||
zap.circuit({
|
||||
import zap : *
|
||||
import cetz.draw : content
|
||||
import "../lib/circuit.typ" : *
|
||||
|
||||
set-style(wire: (stroke: (thickness: 0.025)))
|
||||
|
||||
registerAllCustom();
|
||||
content((-0.7, 0.5), scale($"V"_"DD"$, 60%), anchor: "east")
|
||||
content((-0.7, -2.75), scale($"GND"$, 60%), anchor: "east")
|
||||
|
||||
fet("P0", (0, 0), type: "P", angle: 90deg);
|
||||
fet("P1", (1, 0), type: "P", angle: 90deg);
|
||||
fet("N0", (0.5,-1.25), type: "N", angle: 90deg);
|
||||
fet("N1", (0.5,-2.25), type: "N", angle: 90deg);
|
||||
|
||||
wire((-0.75, 0.5), (1.5, 0.5))
|
||||
wire((-0.75, -2.75), (1.5, -2.75))
|
||||
wire("P0.D", "P1.D")
|
||||
|
||||
node("N2", (horizontal: "N1.D", vertical: "P0.D"))
|
||||
node("N3", "N0.S")
|
||||
wire("N2", "N3")
|
||||
wire("N3", (rel: (0.5, 0)))
|
||||
|
||||
content((horizontal: (rel: (0.65, 0)), vertical: "N3"), scale($"Z"$, 60%))
|
||||
node("4", "P0.S")
|
||||
node("4", "P1.S")
|
||||
node("4", "N1.D")
|
||||
|
||||
content("N0.G", scale($"B"$, 60%), anchor: "east")
|
||||
content("P0.G", scale($"B"$, 60%), anchor: "east")
|
||||
content("N1.G", scale($"A"$, 60%), anchor: "east")
|
||||
content("P1.G", scale($"A"$, 60%), anchor: "east")
|
||||
}),
|
||||
|
||||
[
|
||||
*NAND*
|
||||
|
||||
$overline(A dot B) = Z$
|
||||
],
|
||||
)
|
||||
]
|
||||
|
||||
#bgBlock(fill: colorRealsierung)[
|
||||
#subHeading(fill: colorRealsierung)[Verlustleistung/Verzögerung]
|
||||
|
||||
#image("../images/digitaltechnik/cmosPower.jpg", height: 6cm)
|
||||
|
||||
$t_p ~ C_L / (V_"DD" - V_"Tn")$
|
||||
|
||||
$P_"stat" ~ e^(-V_T)$
|
||||
|
||||
$P_"dyn"~ V_"DD"^2$
|
||||
|
||||
|
||||
*Dynamisch:* Bei Schlaten \
|
||||
1. Kapazitiv Verlustleistung $I_C$ \
|
||||
2. Querstrom Verlustleistung $I_Q$ \
|
||||
|
||||
#zap.circuit({
|
||||
import zap : *
|
||||
import cetz.draw : content
|
||||
import "../lib/circuit.typ" : *
|
||||
@@ -390,309 +671,120 @@
|
||||
node("outNode", (0,0.5))
|
||||
node("inNode", (-0.6,0.5))
|
||||
wire((-1, 0.5), "inNode")
|
||||
wire((0.2, 0.5), "outNode")
|
||||
wire((0.5, 0.5), "outNode")
|
||||
wire((0, -0.5), (0, -1))
|
||||
|
||||
node("N2", (0,-0.5))
|
||||
node("N2", (0,-1))
|
||||
node("N2", (0,1.5))
|
||||
|
||||
wire((-1, -0.5), (0.5, -0.5))
|
||||
wire((-1, -1), (0.5, -1))
|
||||
wire((-1, 1.5), (0.5, 1.5))
|
||||
|
||||
content((-1, 0.5), scale($"X"$, 60%), anchor: "east")
|
||||
content((0.45, 0.5), scale($overline("X")$, 60%), anchor: "east")
|
||||
content((0.8, 0.5), scale($overline("X")$, 60%), anchor: "east")
|
||||
content((-0.9, 1.5), scale($"U"_"DD"$, 60%), anchor: "east")
|
||||
content((-0.9, -0.5), scale($"GND"$, 60%), anchor: "east")
|
||||
content((-0.9, -1), scale($"GND"$, 60%), anchor: "east")
|
||||
}),
|
||||
|
||||
[
|
||||
*Inverter*
|
||||
|
||||
$overline(X)$
|
||||
],
|
||||
- Quer/Kurzschluss Strom $i_q$ \
|
||||
$P_"short" = a_01 f beta_n tau (V_"DD" - 2 V_"Tn")^3$ \
|
||||
$tau$: Kurzschluss/Schaltzeit
|
||||
- Lade Strome des $C_L$ $i_c$
|
||||
$P_"cap" = alpha_01 f C_L V_"DD"^2$
|
||||
*Statisch:* Konstant
|
||||
- Leckstom (weil Diode)
|
||||
- Gatestrom
|
||||
]
|
||||
|
||||
zap.circuit({
|
||||
import zap : *
|
||||
import cetz.draw : content
|
||||
import "../lib/circuit.typ" : *
|
||||
// CMOS
|
||||
#bgBlock(fill: colorRealsierung)[
|
||||
#subHeading(fill: colorRealsierung)[CMOS Verzögerung]
|
||||
|
||||
set-style(wire: (stroke: (thickness: 0.025)))
|
||||
*Inverter*\
|
||||
$t_("p"/"nLH") ~ (C_"L" t_"ox" L_"p/n")/(W_"p/n" mu_"p/n" epsilon(V_"DD" - abs(V_"Tpn"))) $
|
||||
|
||||
registerAllCustom();
|
||||
fet("P0", (0.5,0.25), type: "P", angle: 90deg);
|
||||
fet("P1", (0.5,1.25), type: "P", angle: 90deg);
|
||||
fet("N0", (0,-1), type: "N", angle: 90deg);
|
||||
fet("N1", (1,-1), type: "N", angle: 90deg);
|
||||
#grid(
|
||||
columns: (1fr, 1fr),
|
||||
[
|
||||
*Steigend mit*
|
||||
- Last $C_L$
|
||||
- Oxyddicke $T_"ox"$
|
||||
- Kandlalänge $L_"p/n"$
|
||||
- Schwellspannung $V_"Tp/n"$
|
||||
],
|
||||
[
|
||||
*Sinkend mit*
|
||||
- Kanalweite
|
||||
- Landsträger Veweglichkeit $mu_"p/n"$
|
||||
],
|
||||
|
||||
content((-0.7, 1.75), scale($"V"_"DD"$, 60%), anchor: "east")
|
||||
content((-0.7, -1.5), scale($"GND"$, 60%), anchor: "east")
|
||||
|
||||
content("N0.G", scale($"B"$, 60%), anchor: "east")
|
||||
content("P0.G", scale($"B"$, 60%), anchor: "east")
|
||||
content("N1.G", scale($"A"$, 60%), anchor: "east")
|
||||
content("P1.G", scale($"A"$, 60%), anchor: "east")
|
||||
|
||||
wire((-0.75, -1.5), (1.5, -1.5))
|
||||
wire((-0.75, 1.75), (1.5, 1.75))
|
||||
|
||||
wire("N0.S", "N1.S")
|
||||
node("N2", "P0.D")
|
||||
wire("N2", (horizontal: (), vertical: "N0.S"))
|
||||
node("N3", "N0.D")
|
||||
node("N4", "N1.D")
|
||||
node("N5", "P1.S")
|
||||
node("N6", (horizontal: (), vertical: "N0.S"))
|
||||
|
||||
wire("N2", (horizontal: (rel: (0.5, 0)), vertical: "N2"))
|
||||
|
||||
content((horizontal: (rel: (0.65, 0)), vertical: "N2"), scale($"Y"$, 60%))
|
||||
}),
|
||||
|
||||
[
|
||||
*NOR*
|
||||
|
||||
$overline(A +B) = Y$
|
||||
],
|
||||
|
||||
zap.circuit({
|
||||
import zap : *
|
||||
import cetz.draw : content
|
||||
import "../lib/circuit.typ" : *
|
||||
|
||||
set-style(wire: (stroke: (thickness: 0.025)))
|
||||
|
||||
registerAllCustom();
|
||||
content((-0.7, 0.5), scale($"V"_"DD"$, 60%), anchor: "east")
|
||||
content((-0.7, -2.75), scale($"GND"$, 60%), anchor: "east")
|
||||
|
||||
fet("P0", (0, 0), type: "P", angle: 90deg);
|
||||
fet("P1", (1, 0), type: "P", angle: 90deg);
|
||||
fet("N0", (0.5,-1.25), type: "N", angle: 90deg);
|
||||
fet("N1", (0.5,-2.25), type: "N", angle: 90deg);
|
||||
|
||||
wire((-0.75, 0.5), (1.5, 0.5))
|
||||
wire((-0.75, -2.75), (1.5, -2.75))
|
||||
wire("P0.D", "P1.D")
|
||||
|
||||
node("N2", (horizontal: "N1.D", vertical: "P0.D"))
|
||||
node("N3", "N0.S")
|
||||
wire("N2", "N3")
|
||||
wire("N3", (rel: (0.5, 0)))
|
||||
|
||||
content((horizontal: (rel: (0.65, 0)), vertical: "N3"), scale($"Z"$, 60%))
|
||||
node("4", "P0.S")
|
||||
node("4", "P1.S")
|
||||
node("4", "N1.D")
|
||||
|
||||
content("N0.G", scale($"B"$, 60%), anchor: "east")
|
||||
content("P0.G", scale($"B"$, 60%), anchor: "east")
|
||||
content("N1.G", scale($"A"$, 60%), anchor: "east")
|
||||
content("P1.G", scale($"A"$, 60%), anchor: "east")
|
||||
}),
|
||||
|
||||
[
|
||||
*NAND*
|
||||
|
||||
$overline(A dot B) = Z$
|
||||
],
|
||||
)
|
||||
]
|
||||
|
||||
// CMOS
|
||||
#bgBlock(fill: colorRealsierung)[
|
||||
#subHeading(fill: colorRealsierung)[CMOS Verzögerung]
|
||||
|
||||
*Inverter*\
|
||||
$t_("p"/"nLH") ~ (C_"L" t_"ox" L_"p/n")/(W_"p/n" mu_"p/n" epsilon(V_"DD" - abs(V_"Tpn"))) $
|
||||
|
||||
#grid(
|
||||
columns: (1fr, 1fr),
|
||||
[
|
||||
*Steigend mit*
|
||||
- Last $C_L$
|
||||
- Oxyddicke $T_"ox"$
|
||||
- Kandlalänge $L_"p/n"$
|
||||
- Schwellspannung $V_"Tp/n"$
|
||||
],
|
||||
[
|
||||
*Sinkend mit*
|
||||
- Kanalweite
|
||||
- Landsträger Veweglichkeit $mu_"p/n"$
|
||||
],
|
||||
|
||||
)
|
||||
|
||||
$t_p ~ C_L/(beta(V_"DD" - abs(V_"T")))$
|
||||
|
||||
$t_p ~ C_L/(W(V_"DD" - abs(V_"T")))$
|
||||
]
|
||||
|
||||
#bgBlock(fill: colorState)[
|
||||
#subHeading(fill: colorState)[Latches, Flipflops und Register]
|
||||
]
|
||||
|
||||
#bgBlock(fill: colorState)[
|
||||
#subHeading(fill: colorState)[Timing]
|
||||
|
||||
*Register Bedinungen*
|
||||
|
||||
#cetz.canvas(length: 0.5mm, {
|
||||
import cetz.draw: *
|
||||
|
||||
|
||||
let cycle_time = 38
|
||||
let cycle_start = cycle_time*0.8
|
||||
let cycle_end = cycle_time*4
|
||||
let signal_hight = 10
|
||||
let switch_offset = cycle_time/13
|
||||
let signal_storke = (paint: rgb("#2e2e2e"), thickness: 0.3mm)
|
||||
|
||||
let t_c2q = 0.6
|
||||
let t_setup = 0.6
|
||||
let t_hold = 0.4
|
||||
|
||||
// clk1
|
||||
line((1*cycle_time + switch_offset/2, signal_hight + 1), (1*cycle_time + switch_offset/2, -40), stroke: (paint: rgb("#0004ff"), thickness: 0.4mm, dash: "densely-dashed"))
|
||||
|
||||
// q change
|
||||
line((cycle_time*(t_c2q + 1) + switch_offset/2, -15 + signal_hight + 1), (cycle_time*(t_c2q + 1) + switch_offset/2, -40), stroke: (paint: rgb("#0004ff"), thickness: 0.4mm, dash: "densely-dashed"))
|
||||
|
||||
// d change
|
||||
line((cycle_time*(t_setup + 2) + switch_offset/2, -30 + signal_hight + 1), (cycle_time*(t_setup + 2) + switch_offset/2, -40), stroke: (paint: rgb("#0004ff"), thickness: 0.4mm, dash: "densely-dashed"))
|
||||
|
||||
// clk
|
||||
line((cycle_time*3 + switch_offset/2, signal_hight + 1), (cycle_time*3 + switch_offset/2, -40), stroke: (paint: rgb("#0004ff"), thickness: 0.4mm, dash: "densely-dashed"))
|
||||
|
||||
// hold time
|
||||
line((cycle_time*(3+t_hold) + switch_offset/2, -30 + signal_hight + 1), (cycle_time*(3+t_hold) + switch_offset/2, -40), stroke: (paint: rgb("#0004ff"), thickness: 0.4mm, dash: "densely-dashed"))
|
||||
|
||||
|
||||
content(( cycle_start -7, 5), "clk")
|
||||
|
||||
line((cycle_start,0), (cycle_time,0), (cycle_time + switch_offset,signal_hight), (cycle_time*2, signal_hight), (cycle_time*2 + switch_offset, 0), (cycle_time*3, 0), (cycle_time*3 + switch_offset, 10), (cycle_end, signal_hight), stroke: signal_storke)
|
||||
|
||||
translate((0, -15))
|
||||
content((cycle_start -7, 5), "Q")
|
||||
|
||||
line(
|
||||
(cycle_start,0), (cycle_time*(t_c2q + 1), 0),
|
||||
(cycle_time*(t_c2q + 1) + switch_offset, signal_hight),
|
||||
(cycle_time*(t_c2q + 3),signal_hight), (cycle_time*(t_c2q + 3) + switch_offset, 0),
|
||||
(cycle_end + switch_offset, 0),
|
||||
stroke: signal_storke
|
||||
)
|
||||
line(
|
||||
(cycle_start,signal_hight), (cycle_time*(t_c2q + 1), signal_hight),
|
||||
(cycle_time*(t_c2q + 1) + switch_offset, 0),
|
||||
(cycle_time*(t_c2q + 3),0), (cycle_time*(t_c2q + 3) + switch_offset, signal_hight),
|
||||
(cycle_end + switch_offset, signal_hight),
|
||||
stroke: signal_storke
|
||||
)
|
||||
|
||||
translate((0, -15))
|
||||
content((cycle_start -7, 5), "D")
|
||||
$t_p ~ C_L/(beta(V_"DD" - abs(V_"T")))$
|
||||
|
||||
line(
|
||||
(cycle_start,0), (cycle_time*(t_setup + 2), 0),
|
||||
(cycle_time*(t_setup + 2) + switch_offset, signal_hight), (cycle_end + switch_offset, signal_hight), stroke: signal_storke
|
||||
|
||||
$t_p ~ C_L/(W(V_"DD" - abs(V_"T")))$
|
||||
]
|
||||
|
||||
#linebreak()
|
||||
|
||||
#bgBlock(fill: colorRealsierung)[
|
||||
#subHeading(fill: colorRealsierung)[Verlustleistung]
|
||||
|
||||
$"#Schaltvorgänge"$ : Ganzer High-Low Cycles eines Signals
|
||||
|
||||
#linebreak()
|
||||
|
||||
$"Energie pro Schaltvorgang:" \ "Lade Verlust" + "Geladene Energie" \
|
||||
= E_"stored" + E_"heat" = C_L V_"DD"^2$ (unabhängig von $R_"on"$)
|
||||
|
||||
#linebreak()
|
||||
|
||||
$alpha = "#Schaltvorgänge"/"#Takte (#Clk Flanken)"$
|
||||
|
||||
$P_"cap" = alpha dot f_"clk" dot C dot U_"DD"^2$
|
||||
|
||||
]
|
||||
|
||||
#colbreak()
|
||||
|
||||
#SIPrefixesTable
|
||||
|
||||
#colbreak()
|
||||
#bgBlock(fill: colorBoolscheLogic)[
|
||||
#subHeading(fill: colorBoolscheLogic)[Logik Gatter]
|
||||
|
||||
#grid(columns: (auto, 1fr),
|
||||
row-gutter: 2mm,
|
||||
align(center, box(image("../images/digitaltechnik/logicGates.jpg", height: 6cm, fit: "cover"), clip: true, height: 6cm/4)),
|
||||
align(center+horizon, [*AND* \ $and$]),
|
||||
|
||||
align(center, box(inset: (top: -6cm/4), image("../images/digitaltechnik/logicGates.jpg", height: 6cm, fit: "cover"), clip: true, height: 6cm/4)),
|
||||
align(center+horizon, [*OR* \ $or$]),
|
||||
|
||||
align(center, box(inset: (top: -6cm/4 * 2), image("../images/digitaltechnik/logicGates.jpg", height: 6cm, fit: "cover"), clip: true, height: 6cm/4)),
|
||||
align(center+horizon, [*XOR* \ $xor$]),
|
||||
|
||||
align(center, box(inset: (top: -6cm/4 *3), image("../images/digitaltechnik/logicGates.jpg", height: 6cm, fit: "cover"), clip: true, height: 6cm/4)),
|
||||
align(center+horizon, [*NOT* \ $not$])
|
||||
)
|
||||
line(
|
||||
(cycle_start,signal_hight), (cycle_time*(t_setup + 2), signal_hight),
|
||||
(cycle_time*(t_setup + 2) + switch_offset, 0), (cycle_end + switch_offset, 0), stroke: signal_storke
|
||||
|
||||
#truth-table(
|
||||
outputs: (
|
||||
("AND", (0, 0, 0, 1)),
|
||||
("OR", (0, 1, 1, 1)),
|
||||
("XOR", (0, 1, 1, 0)),
|
||||
),
|
||||
inputs: ("A", "B")
|
||||
)
|
||||
})
|
||||
|
||||
#truth-table(
|
||||
outputs: (
|
||||
("NAND", (1, 1, 1, 0)),
|
||||
("NOR", (1, 0, 0, 0)),
|
||||
("XNOR", (1, 0, 0, 1)),
|
||||
),
|
||||
inputs: ("A", "B")
|
||||
)
|
||||
]
|
||||
]
|
||||
|
||||
|
||||
|
||||
#bgBlock(fill: colorState)[
|
||||
#subHeading(fill: colorState)[Pipeline/Parallele Verarbeitungseinheiten]
|
||||
]
|
||||
|
||||
#bgBlock(fill: colorState)[
|
||||
#subHeading(fill: colorState)[Zustandsautomaten]
|
||||
]
|
||||
|
||||
#colbreak()
|
||||
#bgBlock(fill: colorRealsierung)[
|
||||
#subHeading(fill: colorRealsierung)[Verlustleistung/Verzögerung]
|
||||
|
||||
$t_p ~ C_L / (V_"DD" - V_"Tn")$
|
||||
|
||||
$P_"stat" ~ e^(-V_T)$
|
||||
|
||||
$P_"dyn"~ V_"DD"^2$
|
||||
|
||||
|
||||
*Dynamisch:* Bei Schlaten \
|
||||
1. Kapazitiv Verlustleistung $I_C$ \
|
||||
2. Querstrom Verlustleistung $I_Q$ \
|
||||
|
||||
#zap.circuit({
|
||||
import zap : *
|
||||
import cetz.draw : content
|
||||
import "../lib/circuit.typ" : *
|
||||
|
||||
set-style(wire: (stroke: (thickness: 0.025)))
|
||||
|
||||
registerAllCustom();
|
||||
fet("N0", (0,0), type: "N", angle: 90deg);
|
||||
fet("P0", (0,1), type: "P", angle: 90deg);
|
||||
wire("N0.G", (rel: (-0.1, 0)), (horizontal: (), vertical: "P0.G"), "P0.G")
|
||||
|
||||
node("outNode", (0,0.5))
|
||||
node("inNode", (-0.6,0.5))
|
||||
wire((-1, 0.5), "inNode")
|
||||
wire((0.5, 0.5), "outNode")
|
||||
wire((0, -0.5), (0, -1))
|
||||
|
||||
node("N2", (0,-1))
|
||||
node("N2", (0,1.5))
|
||||
|
||||
wire((-1, -1), (0.5, -1))
|
||||
wire((-1, 1.5), (0.5, 1.5))
|
||||
|
||||
content((-1, 0.5), scale($"X"$, 60%), anchor: "east")
|
||||
content((0.8, 0.5), scale($overline("X")$, 60%), anchor: "east")
|
||||
content((-0.9, 1.5), scale($"U"_"DD"$, 60%), anchor: "east")
|
||||
content((-0.9, -1), scale($"GND"$, 60%), anchor: "east")
|
||||
}),
|
||||
|
||||
- Quer/Kurzschluss Strom $i_q$ \
|
||||
$P_"short" = a_01 f beta_n tau (V_"DD" - 2 V_"Tn")^3$ \
|
||||
$tau$: Kurzschluss/Schaltzeit
|
||||
- Lade Strome des $C_L$ $i_c$
|
||||
$P_"cap" = alpha_01 f C_L V_"DD"^2$
|
||||
*Statisch:* Konstant
|
||||
- Leckstom (weil Diode)
|
||||
- Gatestrom
|
||||
]
|
||||
|
||||
#bgBlock(fill: colorRealsierung)[
|
||||
#subHeading(fill: colorRealsierung)[Verlustleistung]
|
||||
|
||||
$alpha = "#Schaltvorgänge"/"#Takte (#Clk Flanken)"$
|
||||
|
||||
$P_"cap" = alpha dot f_"clk" dot C dot U_"DD"$
|
||||
|
||||
]
|
||||
|
||||
#colbreak()
|
||||
|
||||
#SIPrefixesTable
|
||||
]
|
||||
|
||||
#place(bottom,
|
||||
truth-table(
|
||||
outputs: (
|
||||
("NAND", (1, 1, 1, 0)),
|
||||
("NOR", (1, 0, 0, 0)),
|
||||
("XNOR", (1, 0, 0, 1)),
|
||||
("XOR", (0, 1, 1, 0)),
|
||||
("AND", (0, 0, 0, 1)),
|
||||
("OR", (0, 1, 1, 1)),
|
||||
),
|
||||
inputs: ("A", "B")
|
||||
),
|
||||
float: true
|
||||
)
|
||||
]
|
||||
BIN
src/images/digitaltechnik/IMG_0538.jpg
Normal file
|
After Width: | Height: | Size: 125 KiB |
BIN
src/images/digitaltechnik/IMG_0549.jpg
Normal file
|
After Width: | Height: | Size: 54 KiB |
BIN
src/images/digitaltechnik/IMG_0550.jpg
Normal file
|
After Width: | Height: | Size: 84 KiB |
BIN
src/images/digitaltechnik/IMG_0555.jpg
Normal file
|
After Width: | Height: | Size: 25 KiB |
BIN
src/images/digitaltechnik/cmosPower.jpg
Normal file
|
After Width: | Height: | Size: 153 KiB |
BIN
src/images/digitaltechnik/dlatch.jpg
Normal file
|
After Width: | Height: | Size: 49 KiB |
BIN
src/images/digitaltechnik/dlatch2.jpg
Normal file
|
After Width: | Height: | Size: 173 KiB |
BIN
src/images/digitaltechnik/gateWidth.jpg
Normal file
|
After Width: | Height: | Size: 139 KiB |
BIN
src/images/digitaltechnik/literalMenge.jpg
Normal file
|
After Width: | Height: | Size: 72 KiB |
BIN
src/images/digitaltechnik/literalmenge.png
Normal file
|
After Width: | Height: | Size: 66 KiB |
BIN
src/images/digitaltechnik/logicGates.jpg
Normal file
|
After Width: | Height: | Size: 98 KiB |
BIN
src/images/digitaltechnik/nmos1.jpg
Normal file
|
After Width: | Height: | Size: 73 KiB |
BIN
src/images/digitaltechnik/nmos2.jpg
Normal file
|
After Width: | Height: | Size: 60 KiB |
BIN
src/images/digitaltechnik/nmos3.jpg
Normal file
|
After Width: | Height: | Size: 59 KiB |
BIN
src/images/digitaltechnik/parallel.jpg
Normal file
|
After Width: | Height: | Size: 50 KiB |
BIN
src/images/digitaltechnik/pipeline1.jpg
Normal file
|
After Width: | Height: | Size: 92 KiB |
BIN
src/images/digitaltechnik/pipeline2.jpg
Normal file
|
After Width: | Height: | Size: 84 KiB |
BIN
src/images/digitaltechnik/pmos1.jpg
Normal file
|
After Width: | Height: | Size: 160 KiB |
BIN
src/images/digitaltechnik/pmos2.jpg
Normal file
|
After Width: | Height: | Size: 67 KiB |
BIN
src/images/digitaltechnik/pmos3.jpg
Normal file
|
After Width: | Height: | Size: 60 KiB |
BIN
src/images/digitaltechnik/qmc1.jpg
Normal file
|
After Width: | Height: | Size: 146 KiB |
BIN
src/images/digitaltechnik/qmc2.jpg
Normal file
|
After Width: | Height: | Size: 146 KiB |
BIN
src/images/digitaltechnik/qmc3.jpg
Normal file
|
After Width: | Height: | Size: 141 KiB |
BIN
src/images/digitaltechnik/qmc4.jpg
Normal file
|
After Width: | Height: | Size: 128 KiB |
BIN
src/images/digitaltechnik/qmc5.jpg
Normal file
|
After Width: | Height: | Size: 127 KiB |
BIN
src/images/digitaltechnik/qmc6.jpg
Normal file
|
After Width: | Height: | Size: 190 KiB |