diff --git a/src/cheatsheets/Digitaltechnik.typ b/src/cheatsheets/Digitaltechnik.typ index 32383bb..ef26f48 100644 --- a/src/cheatsheets/Digitaltechnik.typ +++ b/src/cheatsheets/Digitaltechnik.typ @@ -24,13 +24,12 @@ columns: (1fr, 1fr, 1fr), [#align(left, datetime.today().display("[day].[month].[year]"))], [#align(center, counter(page).display("- 1 -"))], - [Thanks to Daniel for the circuit Symbols], [#align(right, image("../images/cc0.png", height: 5mm,))] ) ], ) -#set text(11pt) +#set text(10pt) #let pTypeFill = rgb("#dd5959").lighten(10%); #let nTypeFill = rgb("#5997dd").lighten(10%); @@ -116,8 +115,22 @@ $f: {0,1}^n -> {0,1}$ Variablenmenge: ${x_0, x_1, ..., x_n}$\ - Literalmenge: ${x_0, ..., x_n, LNot(x_0), ... LNot(x_n)}$ \ - $x_0 $ + + Literal-*Menge*: ${x_0, ..., x_n, LNot(x_0), ... LNot(x_n)}$ + + $x_0$: Postives Literal $equiv 1$\ + $LNot(x_0)$: Negatives Literal $equiv 0$\ + + #grid( + columns: (1fr, auto), + [ + Literal-*Länge*: Anzahl der Gattereingänge + + Bei ganzer Schaltung: \ $sum$ Gattereingänge + ], + image("../images/digitaltechnik/literalMenge.jpg", height: 1.6cm), + ) + Einsmenge: $F = {underline(v) in {0,1}^n | f(underline(v)) = 1}$ \ Nullmenge: $overline(F) = {underline(v) in {0,1}^n | f(underline(v)) = 0}$ \ @@ -242,21 +255,89 @@ 5. Wiederhole 3.-5. solange noch was geht ] - #bgBlock(fill: colorState)[ - #subHeading(fill: colorState)[Latches, Flipflops und Register] - #image("../images/digitaltechnik/dlatch2.jpg", height: 6cm) + #colbreak() + + // Voll adierer + #bgBlock(fill: colorBoolscheLogic)[ + #subHeading(fill: colorBoolscheLogic)[Volladierer] + + #grid( + columns: (auto, 1fr), + column-gutter: 2mm, + image("../images/digitaltechnik/va.jpg", height: 1.5cm), + text(8pt, [ + *Generate/Propergated* + + $G = A dot B \ + P = A xor B \ + = A LNot(B) + LNot(A) B $ + + ]) + ) + + $C_"out" = ((A xor B) dot C_"in") + A B $ + + $S = A xor B xor C_"in"$ ] + // FlipFlops + #bgBlock(fill: colorState)[ + #subHeading(fill: colorState)[Latches, Flipflops und Register] + + === D-Latch + #grid( + columns: (auto, auto), + column-gutter: 2mm, + image("../images/digitaltechnik/dlatch3.jpg", height: 2cm), + image("../images/digitaltechnik/dlatch4.jpg", height: 2cm) + ) + + === Register + + #grid( + columns: (auto, auto), + column-gutter: 2mm, + image("../images/digitaltechnik/register1.jpg", height: 1.6cm), + image("../images/digitaltechnik/register2.jpg", height: 1.6cm) + ) + + === Hold/Setup Zeit + #grid( + columns: (auto, 1fr), + column-gutter: 2mm, + image("../images/digitaltechnik/dlatch2.jpg", height: 3cm), + text(7.5pt, [ + $t_"c2q"$: Delay vom Latch \ + $t_"hold"\/t_"setup"$: D muss stabile sein + + *Setup Bedigung* \ + $T_"clk" > T_"c2q" + T_"logic,max"+ T_"setup" $ + + *Hold Bedigung* \ + $T_"c2q" + T_"logic,min" > T_"hold" $ \ + Problem bei unterschiedlichen Register und straight wire + ]) + ) + ] + + // Pipelining #bgBlock(fill: colorState)[ #subHeading(fill: colorState)[Pipeline/Parallele Verarbeitungseinheiten] - #image("../images/digitaltechnik/pipeline1.jpg") + *Pipelining* #image("../images/digitaltechnik/pipeline2.jpg") - #image("../images/digitaltechnik/parallel.jpg", height: 3cm) - ] + #image("../images/digitaltechnik/pipeline1.jpg") - #bgBlock(fill: colorState)[ - #subHeading(fill: colorState)[Zustandsautomaten] + - Split am besten bei Balanced $t_"logic"$ + - $t_"c2q"$ des mitleren Latches kommt dazu + - *Setup Bedigung* \ + $T_"clk" > T_"c2q" + T_"logic,max"+ T_"setup" $ + - *Hold Bedigung* \ + $T_"c2q" + T_"logic,min" > T_"hold" $ \ + Buffer-Gatter einfügen bei Verletzung + + *Parallel Verarbeitung* + #image("../images/digitaltechnik/parallel.jpg", height: 3cm) ] ] #pagebreak() @@ -280,15 +361,19 @@ $L$ wir immer so kleine wie möglich gewählt $= L_"min"$ - $beta_"n/p" = (mu_"n/p" epsilon_0 epsilon_"ox")/(t_"ox") W/L = K'_"n/p" W/L$ - - #grid(columns: (1fr, 1fr), - $C_"G" = epsilon_"ox" epsilon_0 (W L)/t_"ox"$, - $R_"on" = U_"DS"/I_"D"$ - ) + $beta_"n/p" = (mu_"n/p" epsilon_0 epsilon_"ox")/(t_"ox") W/L = K'_"n/p" W/L quad beta = [A/V^2]$ ] ) + #grid(columns: (auto, auto, auto, auto), + column-gutter: 6mm, + $mu_"n" approx 250 dot 10^(-4) m^2/(V s)$, + $mu_"p" approx 100 dot 10^(-4) m^2/(V s)$, + $epsilon_0 approx 8,8541878 dot 10^(-12) (A s)/(V m)$, + $epsilon_"ox" approx 3,9$, + ) + + #table(columns: (1fr, 1fr), fill: (x, y) => if (calc.rem(y, 2) == 1) { tableFillLow } else { tableFillHigh }, @@ -370,8 +455,8 @@ block( inset: (top: 2mm, bottom: 2mm), $I_"Dp" = cases( gap: #0.6em, 0 & 0 > U_"GS" > U_t, - beta_p (U_"GS" - U_t - U_"DS" / 2) U_"DS" quad & cases(delim: #none, U_"GS" <= U_t, 0 > U_"DS" > U_"GS" - U_t), - beta_p/2 (U_"GS" - U_"th")^2 & cases(delim: #none, U_"GS" <= U_t, U_"DS" < U_"GS" - U_t) + -beta_p (U_"GS" - U_t - U_"DS" / 2) U_"DS" quad & cases(delim: #none, U_"GS" <= U_t, 0 > U_"DS" > U_"GS" - U_t), + -beta_p/2 (U_"GS" - U_"th")^2 & cases(delim: #none, U_"GS" <= U_t, U_"DS" < U_"GS" - U_t) )$), grid( @@ -383,8 +468,8 @@ grid( columns: (auto, auto), column-gutter: 2mm, - image("../images/digitaltechnik/pmos1.jpg", height: 2.5cm), - image("../images/digitaltechnik/pmos2.jpg", height: 2.5cm), + image("../images/digitaltechnik/pmos4.jpg", height: 2.5cm), + image("../images/digitaltechnik/pmos3.jpg", height: 2.5cm), ), ) ] @@ -392,6 +477,282 @@ #colbreak() #columns(2, gutter: 2mm)[ + // CMOS Verlust Inverter + #bgBlock(fill: colorRealsierung)[ + #subHeading(fill: colorRealsierung)[CMOS Inverter Verlustleistung] + + #align(center+horizon, image("../images/digitaltechnik/cmosPower.jpg", height: 5cm)) + + #grid( + columns: (1fr, 1fr), + $P_"stat" ~ e^(-V_T)$, + $P_"dyn"~ V_"DD"^2$ + ) + + #table( + columns: (1fr, 1fr), + fill: (x, y) => if (calc.rem(x, 2) == 1) { tableFillLow } else { tableFillHigh }, + + [*Dynamisch* \ Nur beim Schalten], [*Statisch*], + [ + + *Kurzschluss/Quer* $P_"short"\/ I_"short"$ + + #text(8pt, $P_"short" = a_01 f beta_n tau (V_"DD" - 2 V_"Tn")^3$) + + $tau$: Kurzschluss/Schaltzeit + ], + [ + *Leckstrom* + + Durch die NP-Übergänge am FET + + + *Sub Schwellstrom* + ], + [ + *Kapazitiv* $P_C \/ I_C$ \ + Lade Strome des $C_L$ $i_c$ + + $P_"cap" = alpha_01 f C_L V_"DD"^2$ + ], + [ + *Gate-Strom* + + Nicht perfekte Isolations des Gates + ] + ) + + #SeperatorLine + + #grid(columns: (1fr, 1fr), + row-gutter: 1mm, + image("../images/digitaltechnik/verlust1.jpg", height: 2.3cm), + image("../images/digitaltechnik/verlust3.jpg", height: 2.3cm), + image("../images/digitaltechnik/verlust4.jpg", height: 2.3cm), + align(horizon, [ + #text(rgb("#08468d"), [Dyn. Verlustleistung]) + #text(rgb("#067154"), [Stat. Verlustleistung]) + #text(rgb("#a50003"), [Verzögerungs-Zeit]) + ]) + ) + ] + + // Schaltungstheorie + #bgBlock(fill: colorRealsierung)[ + #subHeading(fill: colorRealsierung)[Schaltungstheorie] + + Ohm: $U = R dot I = [V = Omega dot A]$ + + *Kapazität* \ + $tau = R C$ + + Charging: $V_C (t) = V_0 dot (e^(-t/tau))$ + + Discharging: $V_C (t) = V_0 dot (1 - e^(-t/tau))$ + + #grid( + columns: (1fr, 1fr), + column-gutter: 2mm, + row-gutter: 3.5mm, + $q(t) = C dot u(t)$, + $i(t) = C dot (d u)/(d g t)$, + $[C] = F = (A s)/V$, + $E_"C" = q^2/2 C = C/2 u^2$, + $E = integral_(t_1)^(t_2) i(t) u(t)$, + $E = integral_(q_1)^(q_2) chi(q) d q$, + ) + ] + + // CMOS Verzögerung + #bgBlock(fill: colorRealsierung)[ + #subHeading(fill: colorRealsierung)[CMOS Verzögerung] + + *Inverter*\ + $beta_"n/p" = (mu_"n/p" epsilon_0 epsilon_"ox")/(t_"ox") W/L = K'_"n/p" W/L$ + + $C_"G" = epsilon_"ox" epsilon_0 (W L)/t_"ox"$, + + $mu_"n" = 1,6 mu_"p" "bis" 3,5 mu_"p" ==> mu_"n" > mu_"p"$ + + + *Vereinfachung Saturations Bereich* \ + $R_"on" = U_"DS"/I_"D" approx 1/beta(abs(V_"GS")- abs(V_"T"))$ + + #table( + columns: (1fr, 1fr), + fill: (x, y) => if (calc.rem(x, 2) == 1) { tableFillLow } else { tableFillHigh }, + [*Steigend mit*], + [*Sinkend mit*], + [ + - Last $C_L$ + - Oxyddicke $T_"ox"$ + - Kandlalänge $L_"p/n"$ + - Schwellspannung $V_"Tp/n"$ + ], + [ + - Kanalweite + - Landsträger Veweglichkeit $mu_"p/n"$ + ], + + ) + + $t_("p/nLH") ~ (C_"L" t_"ox" L_"p/n")/(W_"p/n" mu_"p/n" epsilon(V_"DD" - abs(V_"Tpn"))) = C_L/(beta(V_"DD" - abs(V_"T"))) $ + ] + + #colbreak() + // CMOS Verlust Gesamt + #bgBlock(fill: colorRealsierung)[ + #subHeading(fill: colorRealsierung)[Verlustleistung] + + $"#Schaltvorgänge"$ : Ganzer High-Low Cycles eines Signals + + #linebreak() + + $"Energie pro Schaltvorgang:" \ "Lade Verlust" + "Geladene Energie" \ + = E_"stored" + E_"heat" = C_L V_"DD"^2$ (unabhängig von $R_"on"$) + + #linebreak() + + $alpha = "#Schaltvorgänge"/"#Takte (#Clk Flanken)"$ + + $P_"cap" = alpha dot f_"clk" dot C dot U_"DD"^2$ + + ] + + // CMOS Circits + #bgBlock(fill: colorRealsierung)[ + #subHeading(fill: colorRealsierung)[CMOS] + $hat(=)$ Complemntary MOS + + #table( + columns: (1fr, 1fr), + scale(75%, + zap.circuit({ + import zap : * + import cetz.draw : content + import "../lib/circuit.typ" : * + + set-style(wire: (stroke: (thickness: 0.025))) + + registerAllCustom(); + fet("N0", (0,0), type: "N", angle: 90deg); + fet("P0", (0,1), type: "P", angle: 90deg); + wire("N0.G", (rel: (-0.1, 0)), (horizontal: (), vertical: "P0.G"), "P0.G") + + node("outNode", (0,0.5)) + node("inNode", (-0.6,0.5)) + wire((-1, 0.5), "inNode") + wire((0.2, 0.5), "outNode") + + node("N2", (0,-0.5)) + node("N2", (0,1.5)) + + wire((-1, -0.5), (0.5, -0.5)) + wire((-1, 1.5), (0.5, 1.5)) + + content((-1, 0.5), scale($"X"$, 60%), anchor: "east") + content((0.45, 0.5), scale($overline("X")$, 60%), anchor: "east") + content((-0.9, 1.5), scale($"U"_"DD"$, 60%), anchor: "east") + content((-0.9, -0.5), scale($"GND"$, 60%), anchor: "east") + }) + ), + [ + *Inverter* + + $overline(X)$ + + ], + + block(height: 3cm, clip: true, inset: (bottom: 1.5cm), scale(75%, zap.circuit({ + import zap : * + import cetz.draw : content + import "../lib/circuit.typ" : * + + set-style(wire: (stroke: (thickness: 0.025))) + + registerAllCustom(); + fet("P0", (0.5,0.25), type: "P", angle: 90deg); + fet("P1", (0.5,1.25), type: "P", angle: 90deg); + fet("N0", (0,-1), type: "N", angle: 90deg); + fet("N1", (1,-1), type: "N", angle: 90deg); + + content((-0.7, 1.75), scale($"V"_"DD"$, 60%), anchor: "east") + content((-0.7, -1.5), scale($"GND"$, 60%), anchor: "east") + + content("N0.G", scale($"B"$, 60%), anchor: "east") + content("P0.G", scale($"B"$, 60%), anchor: "east") + content("N1.G", scale($"A"$, 60%), anchor: "east") + content("P1.G", scale($"A"$, 60%), anchor: "east") + + wire((-0.75, -1.5), (1.5, -1.5)) + wire((-0.75, 1.75), (1.5, 1.75)) + + wire("N0.S", "N1.S") + node("N2", "P0.D") + wire("N2", (horizontal: (), vertical: "N0.S")) + node("N3", "N0.D") + node("N4", "N1.D") + node("N5", "P1.S") + node("N6", (horizontal: (), vertical: "N0.S")) + + wire("N2", (horizontal: (rel: (0.5, 0)), vertical: "N2")) + + content((horizontal: (rel: (0.65, 0)), vertical: "N2"), scale($"Y"$, 60%)) + }))), + + [ + *NOR* + + $LNot(A + B) = Y \ = LNot(A) dot LNot(B)$ + + ], + + block(height: 3cm, clip: true, inset: (bottom: 1.5cm), scale(75%, zap.circuit({ + import zap : * + import cetz.draw : content + import "../lib/circuit.typ" : * + + set-style(wire: (stroke: (thickness: 0.025))) + + registerAllCustom(); + content((-0.7, 0.5), scale($"V"_"DD"$, 60%), anchor: "east") + content((-0.7, -2.75), scale($"GND"$, 60%), anchor: "east") + + fet("P0", (0, 0), type: "P", angle: 90deg); + fet("P1", (1, 0), type: "P", angle: 90deg); + fet("N0", (0.5,-1.25), type: "N", angle: 90deg); + fet("N1", (0.5,-2.25), type: "N", angle: 90deg); + + wire((-0.75, 0.5), (1.5, 0.5)) + wire((-0.75, -2.75), (1.5, -2.75)) + wire("P0.D", "P1.D") + + node("N2", (horizontal: "N1.D", vertical: "P0.D")) + node("N3", "N0.S") + wire("N2", "N3") + wire("N3", (rel: (0.5, 0))) + + content((horizontal: (rel: (0.65, 0)), vertical: "N3"), scale($"Z"$, 60%)) + node("4", "P0.S") + node("4", "P1.S") + node("4", "N1.D") + + content("N0.G", scale($"B"$, 60%), anchor: "east") + content("P0.G", scale($"B"$, 60%), anchor: "east") + content("N1.G", scale($"A"$, 60%), anchor: "east") + content("P1.G", scale($"A"$, 60%), anchor: "east") + }))), + + [ + *NAND* + + $LNot(A dot B) = Z \ = LNot(A) + LNot(B)$ + ], + ) + ] + + #colbreak() // Dotierung #bgBlock(fill: colorRealsierung)[ #subHeading(fill: colorRealsierung)[Dotierung] @@ -515,240 +876,6 @@ */ ] - // CMOS Circits - #bgBlock(fill: colorRealsierung)[ - #subHeading(fill: colorRealsierung)[CMOS] - $hat(=)$ Complemntary MOS - - #table( - columns: (1fr, 1fr), - zap.circuit({ - import zap : * - import cetz.draw : content - import "../lib/circuit.typ" : * - - set-style(wire: (stroke: (thickness: 0.025))) - - registerAllCustom(); - fet("N0", (0,0), type: "N", angle: 90deg); - fet("P0", (0,1), type: "P", angle: 90deg); - wire("N0.G", (rel: (-0.1, 0)), (horizontal: (), vertical: "P0.G"), "P0.G") - - node("outNode", (0,0.5)) - node("inNode", (-0.6,0.5)) - wire((-1, 0.5), "inNode") - wire((0.2, 0.5), "outNode") - - node("N2", (0,-0.5)) - node("N2", (0,1.5)) - - wire((-1, -0.5), (0.5, -0.5)) - wire((-1, 1.5), (0.5, 1.5)) - - content((-1, 0.5), scale($"X"$, 60%), anchor: "east") - content((0.45, 0.5), scale($overline("X")$, 60%), anchor: "east") - content((-0.9, 1.5), scale($"U"_"DD"$, 60%), anchor: "east") - content((-0.9, -0.5), scale($"GND"$, 60%), anchor: "east") - }), - - [ - *Inverter* - - $overline(X)$ - ], - - zap.circuit({ - import zap : * - import cetz.draw : content - import "../lib/circuit.typ" : * - - set-style(wire: (stroke: (thickness: 0.025))) - - registerAllCustom(); - fet("P0", (0.5,0.25), type: "P", angle: 90deg); - fet("P1", (0.5,1.25), type: "P", angle: 90deg); - fet("N0", (0,-1), type: "N", angle: 90deg); - fet("N1", (1,-1), type: "N", angle: 90deg); - - content((-0.7, 1.75), scale($"V"_"DD"$, 60%), anchor: "east") - content((-0.7, -1.5), scale($"GND"$, 60%), anchor: "east") - - content("N0.G", scale($"B"$, 60%), anchor: "east") - content("P0.G", scale($"B"$, 60%), anchor: "east") - content("N1.G", scale($"A"$, 60%), anchor: "east") - content("P1.G", scale($"A"$, 60%), anchor: "east") - - wire((-0.75, -1.5), (1.5, -1.5)) - wire((-0.75, 1.75), (1.5, 1.75)) - - wire("N0.S", "N1.S") - node("N2", "P0.D") - wire("N2", (horizontal: (), vertical: "N0.S")) - node("N3", "N0.D") - node("N4", "N1.D") - node("N5", "P1.S") - node("N6", (horizontal: (), vertical: "N0.S")) - - wire("N2", (horizontal: (rel: (0.5, 0)), vertical: "N2")) - - content((horizontal: (rel: (0.65, 0)), vertical: "N2"), scale($"Y"$, 60%)) - }), - - [ - *NOR* - - $overline(A +B) = Y$ - ], - - zap.circuit({ - import zap : * - import cetz.draw : content - import "../lib/circuit.typ" : * - - set-style(wire: (stroke: (thickness: 0.025))) - - registerAllCustom(); - content((-0.7, 0.5), scale($"V"_"DD"$, 60%), anchor: "east") - content((-0.7, -2.75), scale($"GND"$, 60%), anchor: "east") - - fet("P0", (0, 0), type: "P", angle: 90deg); - fet("P1", (1, 0), type: "P", angle: 90deg); - fet("N0", (0.5,-1.25), type: "N", angle: 90deg); - fet("N1", (0.5,-2.25), type: "N", angle: 90deg); - - wire((-0.75, 0.5), (1.5, 0.5)) - wire((-0.75, -2.75), (1.5, -2.75)) - wire("P0.D", "P1.D") - - node("N2", (horizontal: "N1.D", vertical: "P0.D")) - node("N3", "N0.S") - wire("N2", "N3") - wire("N3", (rel: (0.5, 0))) - - content((horizontal: (rel: (0.65, 0)), vertical: "N3"), scale($"Z"$, 60%)) - node("4", "P0.S") - node("4", "P1.S") - node("4", "N1.D") - - content("N0.G", scale($"B"$, 60%), anchor: "east") - content("P0.G", scale($"B"$, 60%), anchor: "east") - content("N1.G", scale($"A"$, 60%), anchor: "east") - content("P1.G", scale($"A"$, 60%), anchor: "east") - }), - - [ - *NAND* - - $overline(A dot B) = Z$ - ], - ) - ] - - #bgBlock(fill: colorRealsierung)[ - #subHeading(fill: colorRealsierung)[Verlustleistung/Verzögerung] - - #image("../images/digitaltechnik/cmosPower.jpg", height: 6cm) - - $t_p ~ C_L / (V_"DD" - V_"Tn")$ - - $P_"stat" ~ e^(-V_T)$ - - $P_"dyn"~ V_"DD"^2$ - - - *Dynamisch:* Bei Schlaten \ - 1. Kapazitiv Verlustleistung $I_C$ \ - 2. Querstrom Verlustleistung $I_Q$ \ - - #zap.circuit({ - import zap : * - import cetz.draw : content - import "../lib/circuit.typ" : * - - set-style(wire: (stroke: (thickness: 0.025))) - - registerAllCustom(); - fet("N0", (0,0), type: "N", angle: 90deg); - fet("P0", (0,1), type: "P", angle: 90deg); - wire("N0.G", (rel: (-0.1, 0)), (horizontal: (), vertical: "P0.G"), "P0.G") - - node("outNode", (0,0.5)) - node("inNode", (-0.6,0.5)) - wire((-1, 0.5), "inNode") - wire((0.5, 0.5), "outNode") - wire((0, -0.5), (0, -1)) - - node("N2", (0,-1)) - node("N2", (0,1.5)) - - wire((-1, -1), (0.5, -1)) - wire((-1, 1.5), (0.5, 1.5)) - - content((-1, 0.5), scale($"X"$, 60%), anchor: "east") - content((0.8, 0.5), scale($overline("X")$, 60%), anchor: "east") - content((-0.9, 1.5), scale($"U"_"DD"$, 60%), anchor: "east") - content((-0.9, -1), scale($"GND"$, 60%), anchor: "east") - }), - - - Quer/Kurzschluss Strom $i_q$ \ - $P_"short" = a_01 f beta_n tau (V_"DD" - 2 V_"Tn")^3$ \ - $tau$: Kurzschluss/Schaltzeit - - Lade Strome des $C_L$ $i_c$ - $P_"cap" = alpha_01 f C_L V_"DD"^2$ - *Statisch:* Konstant - - Leckstom (weil Diode) - - Gatestrom - ] - - // CMOS - #bgBlock(fill: colorRealsierung)[ - #subHeading(fill: colorRealsierung)[CMOS Verzögerung] - - *Inverter*\ - $t_("p"/"nLH") ~ (C_"L" t_"ox" L_"p/n")/(W_"p/n" mu_"p/n" epsilon(V_"DD" - abs(V_"Tpn"))) $ - - #grid( - columns: (1fr, 1fr), - [ - *Steigend mit* - - Last $C_L$ - - Oxyddicke $T_"ox"$ - - Kandlalänge $L_"p/n"$ - - Schwellspannung $V_"Tp/n"$ - ], - [ - *Sinkend mit* - - Kanalweite - - Landsträger Veweglichkeit $mu_"p/n"$ - ], - - ) - - $t_p ~ C_L/(beta(V_"DD" - abs(V_"T")))$ - - $t_p ~ C_L/(W(V_"DD" - abs(V_"T")))$ - ] - - #linebreak() - - #bgBlock(fill: colorRealsierung)[ - #subHeading(fill: colorRealsierung)[Verlustleistung] - - $"#Schaltvorgänge"$ : Ganzer High-Low Cycles eines Signals - - #linebreak() - - $"Energie pro Schaltvorgang:" \ "Lade Verlust" + "Geladene Energie" \ - = E_"stored" + E_"heat" = C_L V_"DD"^2$ (unabhängig von $R_"on"$) - - #linebreak() - - $alpha = "#Schaltvorgänge"/"#Takte (#Clk Flanken)"$ - - $P_"cap" = alpha dot f_"clk" dot C dot U_"DD"^2$ - - ] - #colbreak() #SIPrefixesTable @@ -757,19 +884,30 @@ #bgBlock(fill: colorBoolscheLogic)[ #subHeading(fill: colorBoolscheLogic)[Logik Gatter] - #grid(columns: (auto, 1fr), - row-gutter: 2mm, + #table(columns: (auto, 1fr), + fill: (x, y) => if (calc.rem(y, 2) == 1) { tableFillLow } else { tableFillHigh }, align(center, box(image("../images/digitaltechnik/logicGates.jpg", height: 6cm, fit: "cover"), clip: true, height: 6cm/4)), - align(center+horizon, [*AND* \ $and$]), + align(center+horizon, [*AND* \ $and space dot$]), align(center, box(inset: (top: -6cm/4), image("../images/digitaltechnik/logicGates.jpg", height: 6cm, fit: "cover"), clip: true, height: 6cm/4)), - align(center+horizon, [*OR* \ $or$]), + align(center+horizon, [*OR* \ $or space +$]), align(center, box(inset: (top: -6cm/4 * 2), image("../images/digitaltechnik/logicGates.jpg", height: 6cm, fit: "cover"), clip: true, height: 6cm/4)), align(center+horizon, [*XOR* \ $xor$]), align(center, box(inset: (top: -6cm/4 *3), image("../images/digitaltechnik/logicGates.jpg", height: 6cm, fit: "cover"), clip: true, height: 6cm/4)), - align(center+horizon, [*NOT* \ $not$]) + align(center+horizon, [*NOT* \ $not space LNot(X)$]) + ) + + #grid( + columns: (auto, 1fr), + column-gutter: 4mm, + row-gutter: 2.5mm, + [XOR], $A LNot(B) + LNot(A) B = A xor B$, + [XNOR], $A B + LNot(A) LNot(B)$, + [NOR], $LNot(A + B) = LNot(A) dot LNot(B)$, + [NAND], $LNot(A dot B) = LNot(A) + LNot(B)$, + ) #truth-table( diff --git a/src/images/digitaltechnik/IMG_0559.jpg b/src/images/digitaltechnik/IMG_0559.jpg new file mode 100644 index 0000000..8fd2a94 Binary files /dev/null and b/src/images/digitaltechnik/IMG_0559.jpg differ diff --git a/src/images/digitaltechnik/dlatch3.jpg b/src/images/digitaltechnik/dlatch3.jpg new file mode 100644 index 0000000..1c90d27 Binary files /dev/null and b/src/images/digitaltechnik/dlatch3.jpg differ diff --git a/src/images/digitaltechnik/dlatch4.jpg b/src/images/digitaltechnik/dlatch4.jpg new file mode 100644 index 0000000..13d5ed3 Binary files /dev/null and b/src/images/digitaltechnik/dlatch4.jpg differ diff --git a/src/images/digitaltechnik/pmos4.jpg b/src/images/digitaltechnik/pmos4.jpg new file mode 100644 index 0000000..3ae98a9 Binary files /dev/null and b/src/images/digitaltechnik/pmos4.jpg differ diff --git a/src/images/digitaltechnik/register1.jpg b/src/images/digitaltechnik/register1.jpg new file mode 100644 index 0000000..6bfb0c6 Binary files /dev/null and b/src/images/digitaltechnik/register1.jpg differ diff --git a/src/images/digitaltechnik/register2.jpg b/src/images/digitaltechnik/register2.jpg new file mode 100644 index 0000000..e8fbf0b Binary files /dev/null and b/src/images/digitaltechnik/register2.jpg differ diff --git a/src/images/digitaltechnik/srlatch.jpg b/src/images/digitaltechnik/srlatch.jpg new file mode 100644 index 0000000..9caeb3a Binary files /dev/null and b/src/images/digitaltechnik/srlatch.jpg differ diff --git a/src/images/digitaltechnik/va.jpg b/src/images/digitaltechnik/va.jpg new file mode 100644 index 0000000..21f92a1 Binary files /dev/null and b/src/images/digitaltechnik/va.jpg differ diff --git a/src/images/digitaltechnik/verlust1.jpg b/src/images/digitaltechnik/verlust1.jpg new file mode 100644 index 0000000..036f946 Binary files /dev/null and b/src/images/digitaltechnik/verlust1.jpg differ diff --git a/src/images/digitaltechnik/verlust2.jpg b/src/images/digitaltechnik/verlust2.jpg new file mode 100644 index 0000000..036f946 Binary files /dev/null and b/src/images/digitaltechnik/verlust2.jpg differ diff --git a/src/images/digitaltechnik/verlust3.jpg b/src/images/digitaltechnik/verlust3.jpg new file mode 100644 index 0000000..6f75f23 Binary files /dev/null and b/src/images/digitaltechnik/verlust3.jpg differ diff --git a/src/images/digitaltechnik/verlust4.jpg b/src/images/digitaltechnik/verlust4.jpg new file mode 100644 index 0000000..9d3dc9c Binary files /dev/null and b/src/images/digitaltechnik/verlust4.jpg differ diff --git a/src/lib/logic.typ b/src/lib/logic.typ index a760452..489fe65 100644 --- a/src/lib/logic.typ +++ b/src/lib/logic.typ @@ -11,7 +11,7 @@ min-height: 0.9, spacing: 0.4, padding: 0.25, - fill: white, + fill: none, stroke: auto, )